Non-volatile memory devices are well known in the art. For example, a split-gate memory cell is disclosed in U.S. Pat. No. 5,029,130 (which is incorporated herein by reference for all purposes). This memory cell has a floating gate and a control gate disposed over and controlling the conductivity of a channel region of the substrate extending between source and drain regions. It is also known to form such memory cells on the same wafer as low voltage (LV) logic devices and/or high voltage (HV) logic devices, where the memory cells and logic devices can share common elements or material layers.
Scaling down the size of the memory cell presents several challenges. For example, it is known to use the same oxide (with the same thickness) under the control gate of the memory cell and the logic gate for the HV logic devices. However, the memory cell current will become too low as the cell diffusion (active area) shrinks, and reducing control gate length to increase cell current will increase array leakage making it difficult to reduce the length of the control gate. In addition, the control gate is used to erase the memory cell through a tunnel oxide separating the control and floating gates. However, if the tunnel oxide is related to the HV device oxide, reducing oxide thickness may cause data retention failures.
U.S. Pat. No. 7,868,375 discloses a split-gate memory cell with four gates: a floating gate and select gate (also called a word line or word line gate) that together control the two portions of the channel region, a coupling gate over the floating gate, and an erase gate over the source region. However, scaling this memory cell configuration down in size is difficult given the extra gate over the floating gate.